The present invention relates generally to a method of processing data by using a storage unit for storing operand information required for executing instructions. The invention also concerns an apparatus or system for carrying out the method, wherein the apparatus is equipped with the storage unit for storing the operand information for executing the instructions.
Referring to FIG. 1 of the accompanying drawings, there is illustrated in the register 10 a format of a storage-to-storage instruction, i.e. an instruction of the type according to which two operand data to be used for an arithmetic operation are stored in a storage and the result of the operation is also placed in the storage. Hereinafter, the instruction of this kind will be referred to as an SS instruction. In FIG. 1, a symbol OP represents an operation code of the SS instruction, L.sub.1 and L.sub.2 represent length codes indicative of the lengths of the two operands, B.sub.1 and B.sub.2 represents the numbers of the general purpose registers (or base registers) used for address determination, and D.sub.1 and D.sub.2 represent displacements.
The leftmost byte address (or leading address) of a first operand is determined as the sum of (B.sub.1)+D.sub.1, while the rightmost byte address (or trailing address) of the operand is determined as the sum of (B.sub.1)+D.sub.1 +L.sub.1, wherein (B.sub.1) represents the contents of the general or base register. In the similar manner, the leading address of a second operand is determined as the sum of (B.sub.2) +D.sub.2 with the trailing address thereof being determined as the sum of (B.sub.2)+D.sub.2 +L.sub.2. These addresses are logical addresses. The arithmetic operation is executed on the basis of the first and second operands, the result of which is loaded in the storage location of the first operand.
FIG. 2a of the accompanying drawings illustrates a flow of successive operations of the SS instructions in a computer of a pipeline control type. In the figure, D, A, L, E, P and S designate different steps or stages of the pipeline processings. It will be noted that processings of the different instructions are sequentially initiated every cycle so that a plurality of instructions can be processed in parallel.
At the stage D, decoding of the instruction and the addition for determining the logical addresses of the operands are performed. At the stage A, the logical addresses of the operands thus determined are translated into corresponding real addresses. At the stage L, the operand data are read out from buffer memory. At the stage E, arithmetic operation or calculation is executed by using the operand data thus obtained. At the stage P, the logical address for storing the result of operation or calculation is translated into the real address. At the stage S, the result of the arithmetic operation or calculation is written in a buffer memory. These stages D, A, L, E, P and S are under the control of a stage control circuit which will be described hereinafter.
In general, in the case of the SS instruction, the operand length is often longer. Further, many of the instructions require rather complicated processings. As a consequence, two or more cycles are required for the arithmetic processing performed at the stage E. In FIG. 2a, it is assumed that a succession of the instructions 1 to 4 each require two cycles for the processings at the stage E. Accordingly, the arithmetic operation of the instruction is processed at the pitch or rate of two cycles at the stage E.
It will be understood that in the case of the data processing unit of the pipeline control type, the processings for a plurality of instructions proceed in an overlapping relation. Consequently, there may arise such a situation in which the reading or fetching of the operand for a succeeding instruction is to be effected in precedence to the writing of the operand for a preceding instruction, e.g. the stage L for the succeeding instruction (for example, instruction 2) precedes the stage S for the preceding instruction (e.g. instruction 1). Under this circumstance, in the case of a data processing unit or system of such an architecture in which a sequential order is maintained in the processings of the instructions, there may arise such a situation in which the operand for a succeeding instruction is to be read out or fetched from a storage location in the course of execution of a preceding instruction or in precedence to data alteration of the storage location which is requested by an execution awaiting instruction. In such a situation, the contradiction or conflict must be detected to thereby cause the operand fetch for the succeeding instruction to be delayed until the data alteration or change of the storage location for the preceding instruction has been completed. More specifically, in the case of the above mentioned example, execution of the stage L for the succeeding instruction has to be delayed until the processing at the stage S for the preceding instruction has been completed, to thereby avoid the possibility of a conflict. This type of processing is generally referred to as OSC (Operand Store Compare) event.
When the condition for the OSC event mentioned above takes place, the operand fetch for the succeeding instruction will have to be delayed until the processing for dealing with the OSC event has been performed, as described above, which means that the pipeline processing is disturbed or adversely influenced, thereby degrading the performance of the data processing unit. FIG. 2b illustrates a situation in which the processings for the OSC event must be performed for all the instructions 1 to 4 shown in FIG. 2a. More specifically, the storage data to be changed by executing the instruction 1 is required by the instruction 2, the storage data to be changed or altered for the execution of the instruction 2 is required by the instruction 3 and so on.
Under the circumstance illustrated in FIG. 2b, the instructions are each processed at the pitch or rate of five cycles. Accordingly, the case illustrated in FIG. 2b involves degradation in the performance corresponding to three cycles when compared with the case described above in conjunction with FIG. 2a.